Input dependent common mode biasing

ABSTRACT

A circuit includes a switched capacitor circuit and a voltage generator circuit. The switched capacitor circuit includes first, second, third, and fourth switches and first and second capacitors. The first capacitor has first and second terminals, the first terminal coupled to the first switch. The second capacitor has first and second terminals, the second terminal coupled to the second switch. The third switch has a terminal coupled to the second terminals of the first and second capacitors. The fourth switch has first and second terminals, the first terminal coupled the terminal of the third switch and to the second terminals of the first and second capacitors. The voltage generator circuit has an output coupled to the second terminal of the fourth switch and is configured to provide a common mode output bias voltage at the second terminal of the fourth switch responsive to a common mode input bias voltage.

TECHNICAL FIELD

This disclosure relates to common mode biasing, and more particularly toinput dependent common mode biasing of a circuit.

BACKGROUND

Some systems measure input voltages for data acquisition or feedbackpurposes. For example, relatively low input voltage measurements (e.g.,less than 10 volts (V)) may be taken from input signals having largecommon mode input biases as compared to the input voltage measurement.In such systems, voltage measuring circuits, such as switched capacitorcircuits, may be used to measure (sample) the input voltages whileeliminating the common mode bias at the input. Sampling input voltagesusing a switched capacitor circuit can generate accurate measurementswhen integrated into a data acquisition system, such as ananalog-to-digital converter (ADC).

SUMMARY

In an ADC, a sampled input voltage may be compared to a referencevoltage for quantization, in which the reference voltage is a lowvoltage having a zero volt or substantially zero volt common modereference bias (also referred to herein as a common mode reference biasvoltage). Also, in some systems, a common node or terminal coupled tocapacitors that are used to sample the input voltage and coupled tocapacitors that are used to sample the reference voltage is set to aconstant low voltage, which creates a much larger voltage drop acrossthe capacitors used to sample the input voltage than across thecapacitors used to sample the reference voltage. This difference involtage drop causes input voltage measurement errors due at least inpart to the voltage coefficient of the capacitors, which leads to achange in capacitance under applied DC voltages.

Disclosed examples may be used to reduce or eliminate such measurementerrors. More particularly, a disclosed voltage generator circuit isconfigured to provide, to the common node or terminal of the samplingcapacitors, a common mode output bias voltage that is based on, e.g., isa function of, the common mode input bias (also referred to herein as acommon mode input bias voltage). In a particular example, the commonmode output bias voltage is half the common mode input bias voltage.Providing a common mode output bias voltage that is dynamicallygenerated responsive to the common mode input bias voltage dynamicallybalances the voltage drop across the capacitors used to sample the inputvoltage and across the capacitors used to sample the reference voltage,thereby reducing or eliminating associated input voltage measurementerrors.

In one example, a circuit includes a switched capacitor circuit and avoltage generator circuit. The switched capacitor circuit includesfirst, second, third, and fourth switches and first and secondcapacitors. The first capacitor has a first terminal coupled to thefirst switch and has a second terminal. The second capacitor has arespective first terminal coupled to the second switch and has arespective second terminal. The third switch has a respective firstterminal coupled to the second terminals of the first and secondcapacitors and has a respective second terminal. The fourth switch has arespective first terminal coupled the first terminal of the third switchand to the second terminals of the first and second capacitors and has arespective second terminal. The voltage generator circuit has an outputcoupled to the second terminal of the fourth switch. The voltagegenerator circuit is configured to provide a common mode output biasvoltage at the second terminal of the fourth switch responsive to acommon mode input bias voltage at a terminal of the first switch.

In another example, a circuit includes a first capacitor having firstand second terminals, a second capacitor having respective first andsecond terminals, and a voltage generator circuit having an output. Thesecond terminals of the first and second capacitors are coupledtogether, in which the circuit is configured to receive an input voltageand a common mode input bias voltage at the first terminal of the firstcapacitor and to receive a reference voltage at the first terminal ofthe second capacitor. The output of the voltage generator circuit iscoupled to the second terminals of the first and second capacitors. Thevoltage generator circuit is configured to provide a common mode outputbias voltage at the second terminals of the first and second capacitors,in which the common mode output bias voltage is based on the common modeinput bias voltage.

In another example, a system includes first and second battery cells, amultiplexer, and an ADC. The multiplexer has inputs coupled to the firstand second battery cells and has outputs. The ADC includes a switchedcapacitor circuit, an integrator circuit, and a voltage generatorcircuit. The switched capacitor circuit includes a first capacitorhaving first and second terminals, first, second, third, fourth, firth,and sixth switches, and a second capacitor. The first and secondswitches are coupled between the outputs of the multiplexer and thefirst terminal of the first capacitor. The second capacitor has arespective first terminal coupled to the third and fourth switches andhas a respective second terminal coupled to the second terminal of thefirst capacitor. The fifth switch has a respective first terminalcoupled to the second terminals of the first and second capacitors andhas a respective second terminal. The sixth switch has a respectivefirst terminal coupled the first terminal of the fifth switch andcoupled to the second terminals of the first and second capacitors, andthe sixth switch has a respective second terminal. The integratorcircuit includes an operational amplifier (op-amp) and a thirdcapacitor. The op-amp has an input and an output, wherein the input ofthe op-amp is coupled to the second terminal of the fifth switch. Thethird capacitor is coupled between the input and the output of theop-amp. The generator circuit has a respective output coupled to thesecond terminal of the sixth switch. The voltage generator circuit isconfigured to provide a common mode output bias voltage at the secondterminal of the sixth switch responsive to a common mode input biasvoltage at a terminal of the first switch.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts an example system that may implement input dependentcommon mode biasing.

FIG. 2 depicts an example circuit that may be implemented in the systemshown in FIG. 1 and that includes a voltage generator circuit forproviding input dependent common mode biasing of a switched capacitorcircuit.

FIG. 3 depicts clock signals for driving switches in the circuit shownin FIG. 2 .

FIG. 4 depicts example curves illustrating input voltage measurementerror versus common mode input bias voltage.

FIG. 5 depicts an example circuit for generating a common mode outputbias voltage, which may be implemented in the circuit shown in FIG. 2 .

FIG. 6 depicts an example high-voltage switch circuit that may beimplemented in the circuit shown in FIG. 2 .

FIG. 7 depicts an example differential amplifier circuit with ahigh-voltage input that may be implemented in the circuit shown in FIG.2 .

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Referring initially to FIG. 1 , which depicts an example system 100 thatmay implement input dependent common mode biasing, according to thepresent disclosure. In one example, system 100 is a battery monitoringsystem. In other examples, the system is any type of power or voltagesource or power supply monitoring system. As illustrated, system 100includes a multicell battery pack 102 and an integrated circuit (IC) 110that monitors the battery pack 102. Battery pack 102 and IC 110 arecoupled to an upper voltage terminal 118 and a lower voltage terminal120 of the system 100. In an example, system 100 is part of an ICpackage that may contain additional elements or components not shown. Inthis example, upper voltage terminal 118 is coupled to a first pin ofthe IC package that receives an upper voltage, and lower voltageterminal 120 is coupled to a second pin of the IC package that receivesa lower voltage. For instance, the lower voltage terminal 120 is coupledto electrical ground 122.

Battery pack 102 includes multiple battery cells 1-N (labeled as 104,106, and 108) coupled or stacked in series. One end (a top) of the stackof (battery) cells is coupled to the upper voltage terminal 118, and anopposite end (a bottom) of the stack of cells is coupled to the lowervoltage terminal 120 and, thereby, to ground 122. Three battery cellsare shown, but battery pack 102 can include more or fewer cells. In aparticular example, battery pack 102 includes 25 4V battery cells, suchthat the top of the stack is at 100V.

IC 110 includes a multiplexer 112 and a delta-sigma ADC 114. Themultiplexer 112 has inputs coupled to first and second terminals of eachbattery cell, and are accordingly referred to herein as battery voltageinputs. The multiplexer 112 has outputs coupled to inputs of the ADC114. The ADC 114 has an output 116. In operation, the ADC 114 ismultiplexed by the multiplexer 112 between battery cell voltages. Moreparticularly, the ADC 114 measures differential battery cell voltagesprovided on the ADC 114 inputs. In an example, voltage measurements aretaken by the ADC 114 in a loop that includes multiple measurement slots.At each slot, the multiplexer 112 provides a different pair ofdifferential input voltages at the inputs of the ADC 114. The ADC 114measures the differential voltages of all the cells 1-N on each loop andprovides, for each measurement, a corresponding digital measurementsignal having a certain bit resolution, e.g., 20 bits, at the output116. The digital measurement signal may be provided to a digital signalprocessor (not shown).

Although not illustrated, the ADC 114 includes an analog modulatorfollowed by digital decimation. Embodiments of the present disclosuremay be implemented in the front end or first stage (first integratorstage) of the analog modulator. The front end stage of the analogmodulator is also referred to herein as a switched capacitor integrator.In an example, the switched capacitor integrator includes a switchedcapacitor circuit that samples the differential input voltages, whichthe ADC converts to the digital measurement signal. In an alternativeembodiment, the IC 110 includes a successive-approximation register(SAR) ADC, instead of the delta-sigma ADC. The SAR ADC includes asample-and-hold circuit having capacitors used to acquire the inputvoltage. The sampling capacitors of the switched capacitor integratorand the sampling capacitors of the sample-and-hold circuit may besensitive to the voltage coefficient problem.

A voltage generator circuit (not shown in FIG. 1 ), according to thepresent disclosure, may be coupled to the capacitors of the switchedcapacitor integrator or the capacitors of the sample-and-hold circuit.The voltage generator circuit may provide a common mode output biasvoltage that is dynamically generated responsive to a common mode inputbias voltage to dynamically balance the voltage drop across thecapacitors used to sample the input voltage relative to the voltage dropacross the capacitors used to sample a reference voltage.

FIG. 2 depicts an example circuit 200 that may be implemented in thesystem 100 shown in FIG. 1 and that includes a voltage generator circuitfor providing input dependent common mode biasing of a switchedcapacitor circuit. For instance, circuit 200 is a switched capacitorintegrator implemented as a front end or first stage of the analogmodulator of ADC 114. As illustrated, circuit 200 includes a switchedcapacitor circuit 202, a voltage generator circuit 204, and anintegrator circuit 206. Circuit 200, as illustrated, may be incorporatedinto an ADC having a differential input configuration. However, inanother example, circuit 200 can be modified for incorporation into anADC having a single-ended input configuration.

The switched capacitor circuit 202 includes capacitors 230, 232, 234,and 236 and switches 208, 210, 226, 228, 238, 240, 242, 244, 246, 248,250, and 252 coupled together as shown via their respective first andsecond terminals. Terminals of capacitors may also be referred to hereinas capacitor terminals. Terminals of switches may also be referred toherein as switch terminals. The first terminals of switches 238, 240,246, and 248 are coupled to outputs of a multiplexer, e.g., themultiplexer 112, to receive differential input voltages V_(in+) andV_(in−), for instance differential battery voltages. Since the batteryvoltages are stacked, the differential battery voltages are superimposedonto a direct current (DC) common mode input bias voltage. In theexample of the stacked battery cells, the differential input batterycell voltage is the difference between a higher voltage V_(in+) at thetop terminal of a cell having its battery voltage measured and a lowervoltage V_(in−) at the bottom terminal of the cell having its batteryvoltage measured. Also, the common mode input bias voltage is thevoltage V_(in−) at the bottom terminal of the battery cell. In aparticular example, the voltage V_(in+) is 100V at a top (first)terminal of a first battery cell. The voltage V_(in−) is 95V at a bottom(second) terminal of the first battery cell. The differential batterycell voltage is 5V (V_(in+)−V_(in−)), and the common mode input biasvoltage is or is substantially 95V (V_(in−)).

The first terminals of switches 242, 244, 250, and 252, are coupled tocircuitry (not shown) that generates first and second reference voltagesV_(ref+) and V_(ref−). In an example, V_(ref+) is 1.2V and V_(ref−) is0V. Further to this example, V_(ref+) and V_(ref−) are not superimposedonto a DC voltage. Accordingly, the differential reference voltage is1.2V (V_(ref+)−V_(ref−)), and the common mode reference bias voltage isor is substantially 0V.

Further to the connectivity of circuit elements of the switchedcapacitor circuit 202, the second terminals of the switches 238 and 240are coupled to the first terminal of the capacitor 230. The secondterminals of the switches 242 and 244 are coupled to the first terminalof the capacitor 232. The second terminals of the switches 246 and 248are coupled to the first terminal of the capacitor 234. The secondterminals of the switches 250 and 252 are coupled to the first terminalof the capacitor 236. The second terminals of the capacitors 230 and 232are coupled to the first terminals of the switches 208 and 228. Thesecond terminals of the capacitors 234 and 236 are coupled to the firstterminals of the switches 210 and 226. The second terminals of switches226 and 228 are coupled together at a common node 260. Responsive toswitches 226 and 228 closing, the second terminals of capacitors 230,232, 234, and 236 are coupled together at the common node 260.

In an example, switches 238, 240, 242, 244, 246, 248, 250, and 252 areeach implemented as one or more transistors, such as one or morefield-effect (FET) transistors or one or more bipolar junctiontransistors (BJTs). In an example, switches 208, 210, 226, and 228 areeach implemented as the switch circuit shown in FIG. 6 . Switches 226and 228 are driven (opened and closed or otherwise controlled) using aclock signal Φ₁. Switches 238, 242, 248, and 252 are driven using aclock signal Φ_(1D), which is a delayed version of clock signal Φ₁.Switches 208 and 210 are driven using a clock signal Φ₂. Switches 240,244, 246, and 250 are driven using a clock signal Φ_(2D), which is adelayed version of clock signal Φ₂. Clock signals Φ₁, Φ_(1D), Φ₂, andΦ_(2D) may be supplied by any suitable clock circuit (not shown). FIG. 3depicts a clock timing diagram 300 illustrating example clock signalsover time for driving switches 208, 210, 226, 228, 238, 240, 242, 244,246, 248, 250, and 252. Namely, a signal 302 represents the clock signalΦ₁. A signal 304 represents the clock signal Φ_(1D). A signal 306represents the clock signal Φ₂. A signal 308 represents the clock signalΦ_(2D).

The voltage generator circuit 204 includes first and second dividerelements 214 and 216 and a common mode bias voltage generator circuit212. The first and second divider elements 214 and 216 each haverespective first and second terminals, and the circuit 212 has an inputand an output. In an example, the divider elements 214 and 216 areswitched capacitors (a switch coupled to a capacitor, with the switchbeing controlled by a clock signal), or the divider elements 214 and 216are fixed resistors. The first terminal of the divider element 214 iscoupled in a manner to receive the common mode input bias voltage,V_(in−), which is associated with or corresponding to the differentialvoltage (V_(in+)−V_(in−)) being measured. For instance, the firstterminal of the divider element 214 is coupled to an output of themultiplexer 112. Moreover, the second terminal of the divider element214 is coupled to the first terminal of the divider element 216. Thesecond terminal of the divider element 216 is coupled to an electricalground 254. The input of the circuit 212 is coupled to the secondterminal of the divider element 214 and is coupled to the first terminalof the divider element 216. The output of the circuit 212 is coupled tothe common node 260. In an example, the voltage generator circuit 204 isimplemented as the circuit shown in FIG. 5 .

The integrator circuit 206 includes an operational amplifier (op-amp)218 and capacitors 222 and 224. The capacitors 222 and 224 each haverespective first and second terminals. The op-amp 218 has differential(first and second) inputs 220 and (first and second) outputs 258 and256. The second terminal of the switch 208 is coupled to the firstterminal of the capacitor 222 and to the first (negative) input of theop-amp 218. The second terminal of the switch 210 is coupled to thesecond terminal of the capacitor 224 and to the second (positive) inputof the op-amp 218. The second terminal of the capacitor 222 is coupledto the first (positive) output 258 of the op-amp 218. The secondterminal of the capacitor 224 is coupled to the second (negative) output256 of the op-amp 218. In an example, the integrator circuit 206 isimplemented as the circuit shown in FIG. 7 , which includes a highvoltage (HV) input circuit that may be used to implement thedifferential inputs 220 of the op-amp 218. For instance, a high voltageis greater than 10V.

During operation, f the circuit 200, responsive to the closing of theswitches 208, 210, 226, 228, 238, 240, 242, 244, 246, 248, 250, and 252under the control of their respective clock signals (e.g., according tothe clock timing diagram 300 of FIG. 3 ), generates a differentialvoltage at outputs 258 and 256 that represents a scaled combination ofthe input voltage (V_(in+)−V_(in−)) and the reference voltage(V_(ref+)−V_(ref−)). In this manner the input voltage and referencevoltage can accumulate at the outputs 258 and 256 (represented byV_(OUT+)−V_(OUT−)) and integrate over time. The polarity of theintegration function can be controlled by a feedback term (not shown) tocreate a delta-sigma modulation function.

The common mode input bias voltage V_(in−)(associated with orcorresponding to the differential voltage being measured), is receivedat the first terminal of the divider element 214. The common mode inputbias voltage is divided down by the divider elements 214 and 216, inwhich a divided common mode input bias voltage is provided at the inputof the circuit 212. Responsive to receiving the divided common modeinput bias voltage, the circuit 212 provides a common mode output biasvoltage, V_(CM), to the common node 260, in which V_(CM) is based on,e.g., is a function of V_(in−). For example, V_(CM) is half of V_(in−).Since V_(CM) is dynamically generated responsive to or based on thecurrent common mode input bias voltage V_(in−), as opposed to beingstatic, input voltage measurement errors due to the voltage coefficientof the capacitors is reduced or eliminated.

FIG. 4 depicts a diagram 400 including example curves 406 and 408illustrating input voltage measurement error versus common mode inputbias voltage. Voltage measurement error is shown along the Y axis 402 involts, and common mode input bias voltage is shown along the X-axis 404in volts. Curve 406 corresponds to a fixed common mode bias voltage,e.g., 0.6 V, being applied at the common node 260. Curve 408 correspondsto the voltage generator circuit 204 applying an adaptive or dynamiccommon mode output bias voltage V_(CM) at the common node 260. As shownin curve 406, the input voltage measurement error is over 5 millivolts(mV) when an 80V common mode input bias voltage is present, which cancause significant issues in some systems. However, as reflected by curve408, the input voltage measurement error is significantly reduced by theinclusion of the voltage generator circuit 204.

FIG. 5 depicts an example circuit 500 for generating a common modeoutput bias voltage, which may be implemented in the circuit shown inFIG. 2 . The voltage generator circuit 204 of FIG. 2 may be implementedas circuit 500. As shown, circuit 500 includes a multiplexer 502, firstand second divider elements 504 and 506, and a common mode bias voltagegenerator circuit 540. However, in an alternative example, circuit 500does not include the multiplexer 502. The first and second dividerelements 504 and 506 each have respective first and second terminals,and the multiplexer 502 has inputs labeled 1 to N, another input labeledV_(select), and an output. The divider elements 214 and 216 may beswitched capacitors or fixed resistors.

In an example, the inputs 1 to N of the multiplexer 502 are coupled tothe battery terminals of the cells of the multi-cell battery pack 102.The first terminal of the divider element 504 is coupled to the outputof the multiplexer 502. The second terminal of the divider element 504is coupled to the first terminal of the divider element 506. The secondterminal of the divider element 506 is coupled to electrical ground 510.The V_(select) input is used to control the selection one of the inputs1 to N to provide, to the first terminal of the divider element 504, thecommon mode input bias voltage V_(in−) associated with or correspondingto the differential voltage being measured.

The common mode bias voltage generator circuit 540 includes a(transconductance) amplifier 508 having a transconductance g_(m), acurrent source 512 providing a current I_(ref), transistors 514, 516,518, 520, 522, and 524, capacitors 526 and 528, and resistors 530 and532. Amplifier 508 has a first (positive) input, a second (negative)input, power supply lines, and an output. The current source 512,capacitors 526 and 528, and resistors 530 and 532 each have respectivefirst and second terminals. The transistors 514, 516, 518, 520, 522, and524 are FETs, each having respective first and second terminals (sourceand drain) and a respective control terminal (gate). Terminals ofresistors may also be referred to herein as resistor terminals.Terminals of a current source may also be referred to herein as currentsource terminals. Terminals of transistors may also be referred toherein as transistor terminals.

In this particular example, transistors 514, 516, and 518 are P-channelmetal-oxide-semiconductor field-effect transistors (MOSFETS), andtransistors 520, 522, and 524 are N-channel MOSFETS. Also, transistors514, 516, and 524 are drain-extended transistors that can withstandhigher voltages than transistors 518, 520, and 522.

As illustrated, the negative input of amplifier 508 is coupled to thesecond terminal of the divider element 504 and to the first terminal ofthe divider element 506. One of the power supply lines of the amplifier508 is coupled to a power supply that provides a voltage V_(LV), e.g.,5V, and the other power supply line is coupled to electrical ground 510.The transistor 514 is diode-connected between the current source 512 anda power supply that provides a voltage V_(HV), e.g., 100V. Namely, thesource of transistor 514 is coupled to the power supply that providesV_(HV), and the drain and gate of the transistor 514 are coupledtogether and to the first terminal of the current source 512 and thegate of the transistor 516. The second terminal of the current source512 is coupled to ground 510.

The source of the transistor 516 is coupled to the power supply thatprovides V_(HV). The drain of the transistor 516 is coupled to thesource of the transistor 518 and the first terminal of the capacitor526, from which is defined or extends a first output 534 of the commonmode bias voltage generator circuit 540. Transistors 518, 520, and 522are diode-connected in series between the transistor 516 and thetransistor 524, Namely, the gate and drain of transistor 518 are coupledto the gate and drain of transistor 520. The source of transistor 520 iscoupled to the gate and drain of transistor 522, from which is definedor extends a second output 536 of the common mode bias voltage generatorcircuit 540. The source of the transistor 522 is coupled to the drain ofthe transistor 524, the first terminal of the capacitor 528, the secondterminal of the capacitor 526, and the first terminal of the resistor530, from which is defined or extends a third output 538 of the commonmode bias voltage generator circuit 540. The second terminal of thecapacitor 528 is coupled to the output of the amplifier 508 and to thegate of the transistor 524. The source of the transistor 524 is coupledto ground 510. The second terminal of the resistor 530 is coupled to thefirst terminal of the resistor 532 and to the positive input of theamplifier 508. The second terminal of the resistor 532 is coupled toground 510.

A first voltage V_(PWR) is provided at the output 534. The common modeoutput bias voltage V_(CM) is provided at the output 536. A secondvoltage V_(GND) is provided at the output 538. As illustrated, V_(PWR)is two diode drop voltages above V_(CM), and V_(GND) is one diode dropvoltage below V_(CM). A diode drop voltage, in this case, is the voltagedrop between the source and drain of a diode-connected transistor, e.g.,about 0.6V. Also, V_(CM) is about half of the common mode input biasvoltage V_(in−) associated with or corresponding to the differentialvoltage being measured.

During operation of the circuit 500, the selected input voltage frommultiplexer 502 is continually monitored and buffered to provide avoltage divided representation of the selected input voltage at theoutput V_(CM) (536). The term buffered is used to describe the operationof transforming a high impedance voltage at the (common terminal) outputof the (voltage) divider elements 504 and 506 to low impedance voltagesV_(PWR), V_(CM), and V_(GND) respectively at the outputs 534, 536, and538 of the circuit 540. Other circuit implementations can be used suchthat the circuit 540 is configured to receive a divided common modeinput bias voltage (at the common terminal of the of the dividerelements 504 and 506) and to provide a buffered and lower impedancerepresentation of the divided common mode input bias voltage as thecommon mode output bias voltage V_(CM) and the accompanying voltagesV_(PWR) and V_(GND).

FIG. 6 depicts an example high-voltage switch circuit 600 that may beimplemented in the circuit shown in FIG. 2 . Any one or each of theswitches 208, 210, 226, and 228 of FIG. 2 may be implemented as circuit600. As shown, circuit 600 includes an inverter 602, an inverter 604,capacitors 606 and 608, and a high voltage shifted switch 610. Inverters602 and 604 each have a respective input, a respective output, and firstand second power supply lines. Capacitors 606 and 608 have respectivefirst and second terminals.

The input of the inverter 602 is coupled to a clock circuit (not shown)to receive a clock signal, e.g., Φ₁ or Φ₂ depending on where the switchcircuit is coupled within circuit 200. The output of the inverter 602 iscoupled to the input of the inverter 604 and to the first terminal ofthe capacitor 608. The output of the inverter 604 is coupled to thefirst terminal of the capacitor 606. One power supply line of each ofthe inverter 602 and the inverter 604 is coupled to a power supply thatprovides a voltage V_(LV), e.g., 5V. The other power supply line of eachof the inverter 602 and the inverter 604 is coupled to electrical ground622.

The high voltage shifted switch 610 includes transistors 612, 614, 616,618, and 620. In this particular example, transistors 612 and 614 areP-channel MOSFETS, and transistors 616, 618, and 620 are N-channelMOSFETS. Also, since the transistors 612, 614, 616, 618, and 620 arepowered by a voltage domain of about 1.8V (e.g., V_(PWR)−V_(GND)), noneof these transistors need to be drain-extended transistors. Asillustrated, the sources of transistors 612 and 614 are coupled togetherand to the output 534 to receive V_(PWR). The gate of the transistor 612is coupled to the gate of the transistor 616, to the drains of thetransistors 614 and 618, to the second terminal of the capacitor 606,and to the gate of the transistor 620. An example clock signal Φ_(1HV)derived or provided responsive to the clock signal Φ₁ (or an exampleclock signal Φ_(2HV) derived or provided responsive to the clock signalΦ₂) is provided to the gate of the transistor 620.

The gate of the transistor 614 is coupled to the gate of the transistor618, to the drains of the transistors 612 and 616, and to the secondterminal of the capacitor 608. The sources of the transistors 616 and618 are coupled together and coupled to the output 538 to receiveV_(GND). The transistor 620 serves as the switching transistor. Forexample, where circuit 600 is implemented as the switch 208 of FIG. 2 ,the source of the transistor 620 is coupled to the second terminals ofthe capacitors 230 and 232, and the drain of the transistor 620 iscoupled to the first terminal of the capacitor 222 and coupled to thenegative input of the op-amp 218.

During operation of the circuit 600, the common mode voltage V_(CM)(536) can be selected when the switch 620 is closed and unselected whenthe switch 620 is open. In this way, the low voltage switch 620 isconnected to a high voltage source (V_(CM)) and effectively AC coupledto the low voltage clock sources Φ₁ or Φ₂. In combination, the circuitrycreates an effective high voltage switch (610) using only high voltagecapacitors (608 and 606).

FIG. 7 depicts an example integrator amplifier circuit 700 including adifferential amplifier circuit 704 having as its differential inputs ahigh-voltage input circuit 702, which may be implemented in the circuitshown in FIG. 2 . Circuit 700 further includes a current source 706 thathas first and second terminals and that generates a current I_(ref). Forinstance, circuit 700 represents part of an integrator circuit (butwithout the capacitors), such as the integrator circuit 206. In thisexample, op-amp 218 having differential inputs 220 is implemented asdifferential amplifier 704 having the circuit 702 as its differentialinputs.

As illustrated, the first terminal of the current source 706 is coupledto electrical ground 708. The high-voltage input circuit 702 includestransistors 710, 712, 714, 716, 718, and 720. The differential amplifier704 includes transistors 722, 724, 726, 728, 730, 732, 734, and 736. Asshown, all the transistors 710-720 of the circuit 702 are P-channelMOSFETs, with the transistors 718 and 720 being drain-extendedtransistors. Transistors 722-728 of the circuit 704 are P-channelMOSFETs, and transistors 730-736 of the circuit 704 are N-channelMOSFETs.

As illustrated for the circuit 702, the sources of the transistors 710and 712 are coupled to a power supply that provides a voltage V_(PWR),for instance to the output 534 of circuit 500. The gate of thetransistor 710 is coupled to the drain of the transistor 710, to thesecond terminal of the current source 706, and to the gate of thetransistor 712. The drain of transistor 712 is coupled to the sources oftransistors 714 and 716. The gate of the transistor 714 is coupled tothe second terminal of the switch 208 to receive V_(IN−). The gate ofthe transistor 716 is coupled to the second terminal of the switch 210to receive V_(IN+). The integrator amplifier 700 operates in a closedfeedback loop to maintain the difference between V_(IN+)−V_(IN−) atappreciably or substantially zero voltages. The drain of the transistor714 is coupled to the source of the transistor 718, and the drain of thetransistor 716 is coupled to the source of the transistor 720. The gatesof the transistors 718 and 720 are coupled together and coupled to theoutput 538 to receive V_(GND).

As illustrated for the circuit 704, sources of the transistors 722 and724 are coupled to a power supply that provides a voltage V_(LV), e.g.,2V. The gates of the transistors 722 and 724 are coupled together andare controlled or biased by a voltage V_(bias1). The drain of thetransistor 722 is coupled to the source of the transistor 726. The drainof the transistor 724 is coupled to the source of the transistor 728.The gates of the transistors 726 and 728 are coupled together and arecontrolled or biased by a voltage V_(bias2). The drains of thetransistors 726 and 730 are coupled together, at which a voltageV_(OUT−) is provided. The drains of the transistors 728 and 732 arecoupled together, at which a voltage V_(OUT+) is provided. Theintegrator amplifier 700 operates in a closed feedback loop to maintaina difference voltage between V_(OUT+)−V_(OUT−). to satisfy therequirement that V_(IN+)−V_(IN−) equals to zero volts. The gates of thetransistors 730 and 732 are coupled together and are controlled orbiased by the voltage V_(bias2). The source of the transistor 730 iscoupled to the drains of the transistors 720 and 734. The source of thetransistor 732 is coupled to the drains of the transistors 718 and 736.The gates of the transistors 734 and 736 are coupled together and arecontrolled or biased by the voltage V_(bias3). The source of thetransistor 734 is coupled to ground 708. The source of the transistor736 is coupled to ground 708.

During operation of the circuit 700, the integration function of thedelta-sigma modulation process is implemented. The fully differentialamplifier 700 provides the active circuitry needed to perform theintegration function described previously. The HV differential amplifierinput 702 provides the necessary circuitry to interface the integratoramplifier 700 to the high voltage common mode V_(CM) voltage level atthe output 536.

In the description and in the claims, the terms “including” and “having”and variants thereof are intended to be inclusive in a manner similar tothe term “comprising” unless otherwise noted. Unless otherwise stated,“about,” “approximately,” or “substantially” preceding a value means+/−10 percent of the stated value. In another example, “about,”“approximately,” or “substantially” preceding a value means +/−5 percentof the stated value. In another example, “about,” “approximately,” or“substantially” preceding a value means +/−1 percent of the statedvalue.

The term “couple”, “coupled”, “couples”, and variants thereof, as usedherein, may cover connections, communications, or signal paths thatenable a functional relationship consistent with this description. Forexample, if device A generates a signal to control device B to performan action, in a first example device A is coupled to device B, or in asecond example device A is coupled to device B through interveningcomponent C if intervening component C does not substantially alter thefunctional relationship between device A and device B such that device Bis controlled by device A via the control signal generated by device A.Moreover, the terms “couple”, “coupled”, “couples”, or variants thereof,includes an indirect or direct electrical or mechanical connection.

A device that is “configured to” perform a task or function may beconfigured (e.g., programmed and/or hardwired) at a time ofmanufacturing by a manufacturer to perform the function and/or may beconfigurable (or re-configurable) by a user after manufacturing toperform the function and/or other additional or alternative functions.The configuring may be through firmware and/or software programming ofthe device, through a construction and/or layout of hardware componentsand interconnections of the device, or a combination thereof.

Although not all separately labeled in the FIGS., components or elementsof systems and circuits illustrated therein have one or more conductorsor terminus that allow signals into and/or out of the components orelements. The conductors or terminus (or parts thereof) may be referredto herein as pins, pads, terminals (including input terminals, outputterminals, reference terminals, and ground terminals, for instance),inputs, outputs, nodes, and interconnects.

As used herein, a “terminal” of a component, device, system, circuit,integrated circuit, or other electronic or semiconductor component,generally refers to a conductor such as a wire, trace, pin, pad, orother connector or interconnect that enables the component, device,system, etc., to electrically and/or mechanically connect to anothercomponent, device, system, etc. A terminal may be used, for instance, toreceive or provide analog or digital electrical signals (or simplysignals) or to electrically connect to a common or ground reference.Accordingly, an input terminal or input is used to receive a signal fromanother component, device, system, etc. An output terminal or output isused to provide a signal to another component, device, system, etc.Other terminals may be used to connect to a common, ground, or voltagereference, e.g., a reference terminal or ground terminal. A terminal ofan IC or a PCB may also be referred to as a pin (a longitudinalconductor) or a pad (a planar conductor). A node refers to a point ofconnection or interconnection of two or more terminals. An examplenumber of terminals and nodes may be shown. However, depending on aparticular circuit or system topology, there may be more or fewerterminals and nodes. However, in some instances, “terminal”, “node”,“interconnect”, “pad”, and “pin” may be used interchangeably.

Modifications are possible in the described embodiments, and otherembodiments are possible, within the scope of the claims.

What is claimed is:
 1. A circuit comprising: a switched capacitorcircuit including: a first switch; a first capacitor having a firstterminal coupled to the first switch and having a second terminal; asecond switch; a second capacitor having a respective first terminalcoupled to the second switch, and having a respective second terminal; athird switch having a respective first terminal coupled to the secondterminals of the first and second capacitors, and having a respectivesecond terminal; and a fourth switch having a respective first terminalcoupled the first terminal of the third switch and to the secondterminals of the first and second capacitors, the fourth switch having arespective second terminal; and a voltage generator circuit having anoutput coupled to the second terminal of the fourth switch, the voltagegenerator circuit configured to provide a common mode output biasvoltage at the second terminal of the fourth switch responsive to acommon mode input bias voltage at a terminal of the first switch.
 2. Thecircuit of claim 1, further comprising an integrator circuit including:an operational amplifier (op-amp) having an input and a respectiveoutput, the input of the op-amp coupled to the second terminal of thethird switch; and a third capacitor coupled between the input and theoutput of the op-amp.
 3. The circuit of claim 1, wherein the voltagegenerator circuit is configured to provide a first voltage at a secondoutput and to provide a second voltage at a third output, in which thefirst voltage is one or more diode drop voltages above the common modeoutput bias voltage, and the second voltage is one or more diode dropvoltages below the common mode output bias voltage.
 4. The circuit ofclaim 1, wherein the voltage generator circuit includes: a first dividerelement having respective first and second terminals; a second dividerhaving a respective first terminal coupled to the second terminal of thefirst divider element; and a common mode bias voltage generator circuitcoupled to second terminal of the first divider element and coupled tothe first terminal of the second divider element, the common mode biasvoltage generator circuit configured to provide the common mode outputbias voltage at the second terminal of the fourth switch responsive to avoltage at the first terminal of the first divider element, in which thevoltage is representative of the common mode input bias voltage.
 5. Thecircuit of claim 4, wherein the common mode bias voltage generatorcircuit is configured to receive a divided common mode input biasvoltage and to provide a buffered and lower impedance representation ofthe divided common mode input bias voltage as the common mode outputbias voltage.
 6. The circuit of claim 1, wherein the common mode outputbias voltage is half the common mode input bias voltage.
 7. The circuitof claim 1, further comprising an analog-to-digital converter (ADC) thatincludes the switched capacitor circuit and the voltage generatorcircuit as a first stage of the ADC.
 8. The circuit of claim 7 in whichthe ADC is a delta-sigma ADC.
 9. The circuit of claim 7, furthercomprising a multiplexer having battery voltage inputs and having arespective output coupled to an input of the ADC.
 10. A circuitcomprising: a first capacitor having first and second terminals; asecond capacitor having respective first and second terminals, thesecond terminals of the first and second capacitors are coupledtogether, in which the circuit is configured to receive an input voltageand a common mode input bias voltage at the first terminal of the firstcapacitor and to receive a reference voltage at the first terminal ofthe second capacitor; and a voltage generator circuit having an outputcoupled to the second terminals of the first and second capacitors, thevoltage generator circuit configured to provide a common mode outputbias voltage at the second terminals of the first and second capacitors,in which the common mode output bias voltage is based on the common modeinput bias voltage.
 11. The circuit of claim 10, wherein the common modeoutput bias voltage is half the common mode input bias voltage.
 12. Thecircuit of claim 10, further comprising an integrator circuit including:an operational amplifier (op-amp) having an input and a respectiveoutput, the input of the op-amp coupled to the second terminal of thethird switch; and a third capacitor coupled between the input and theoutput of the op-amp.
 13. The circuit of claim 10, wherein the voltagegenerator circuit includes: a first divider element having respectivefirst and second terminals; a second divider having a respective firstterminal coupled to the second terminal of the first divider element;and a common mode bias voltage generator circuit coupled to secondterminal of the first divider element and coupled to the first terminalof the second divider element, the common mode bias voltage generatorcircuit configured to provide the common mode output bias voltage at thesecond terminal of the fourth switch responsive to a voltage at thefirst terminal of the first divider element, in which the voltage isrepresentative of the common mode input bias voltage, and the commonmode bias voltage generator circuit is configured to provide a firstvoltage at a second output and to provide a second voltage at a thirdoutput, in which the first voltage is one or more diode drop voltagesabove the common mode output bias voltage, and the second voltage is oneor more diode drop voltages below the common mode output bias voltage.14. The circuit of claim 13, wherein the common mode bias voltagegenerator circuit is configured to receive a divided common mode inputbias voltage and to provide a buffered and lower impedancerepresentation of the divided common mode input bias voltage as thecommon mode output bias voltage.
 15. The circuit of claim 10, furthercomprising: an analog-to-digital converter (ADC) that includes theswitched capacitor circuit and the voltage generator circuit as a firststage of the ADC; and a multiplexer having battery voltage inputs andhaving a respective output coupled to an input of the ADC.
 16. A systemcomprising: first and second battery cells; a multiplexer having inputscoupled to the first and second battery cells and having outputs; and ananalog-to-digital converter (ADC) including: a switched capacitorcircuit including: a first capacitor having first and second terminals;first and second switches coupled between the outputs of the multiplexerand the first terminal of the first capacitor; third and fourthswitches; a second capacitor having a respective first terminal coupledto the third and fourth switches and having a respective second terminalcoupled to the second terminal of the first capacitor; a fifth switchhaving a respective first terminal coupled to the second terminals ofthe first and second capacitors and having a respective second terminal;and a sixth switch having a respective first terminal coupled the firstterminal of the fifth switch and coupled to the second terminals of thefirst and second capacitors, the sixth switch having a respective secondterminal; an integrator circuit including: an operational amplifier(op-amp) having an input and an output, the input of the op-amp coupledto the second terminal of the fifth switch; and a third capacitorcoupled between the input and the output of the op-amp; and a voltagegenerator circuit having a respective output coupled to the secondterminal of the sixth switch, the voltage generator circuit configuredto provide a common mode output bias voltage at the second terminal ofthe sixth switch responsive to a common mode input bias voltage at aterminal of the first switch.
 17. The system of claim 16, wherein theADC is a delta-sigma ADC that includes an analog modulator that includesthe switched capacitor circuit, the integrator circuit, and the voltagegenerator circuit as a first stage of the analog modulator.
 18. Thesystem of claim 16, wherein the ADC is a successive-approximationregister ADC.
 19. The system of claim 16, wherein the common mode outputbias voltage is half the common mode input bias voltage.
 20. The systemof claim 16, wherein the voltage generator circuit includes: a firstdivider element having respective first and second terminals; a seconddivider having a respective first terminal coupled to the secondterminal of the first divider element; and a common mode bias voltagegenerator circuit having a respective input coupled to the secondterminal of the first divider element and coupled to the first terminalof the second divider element, having a first output coupled to thesecond terminal of the sixth switch, having a second output coupled tothe fifth and sixth switches, and having a third output coupled to thefifth and sixth switches, the common mode bias voltage generator circuitconfigured to: provide the common mode output bias voltage at firstoutput responsive to a voltage at the first terminal of the firstdivider element, in which the voltage is representative of the commonmode input bias voltage; provide a first voltage at the second output;and provide a second voltage at the third output, in which the firstvoltage is one or more diode drop voltages above the common mode outputbias voltage, and the second voltage is one or more diode drop voltagesbelow the common mode output bias voltage.